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ICE2QS02G quasi-resonant pwm controller never stop thinking. power management & supply datasheet version 2.0, 13 june 2008
edition 13 june 2008 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted charac- teristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infi- neon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representat ives worldwide: see our webpage at http:// www.infineon.com coolmos?, coolset? are trademarks of infineon technologies ag. 13 june 2008 revision history: no datasheet previous version: page subjects (major changes since last revision)
version 2.0 3 13 june 2008 ICE2QS02G quasi-resonant pwm controller pg-dso-8 ICE2QS02G product highlights ? quasi-resonant operation for hi gher efficiency and better emi ? digital frequency reduction for higher average efficiency ? optimized for applications with auxiliary converter ? various protection features with latch mode and auto-restart mode ? adjustable blanking time for over load protection and adjustable restart time ? pb-free lead plating; rohs compliant features ? quasi-resonant operation ? load dependent digital frequency reduction ? built-in digital soft-start ? cycle-by-cycle peak current limitation with built-in leading edge blanking time ? vcc undervoltage protection ? mains undervoltage protection with adjustable hysteresis ? foldback point correction with digitalized sensing and control circuits ? over load protection with adjustable blanking time ? adjustable restart time after over load protection ? adjustable output overvoltage protection with latch mode ? short-winding protection with latch mode ? maximum on time limitation ? maximum switching period limitation description ICE2QS02G is a second generation quasi-resonant pwm controller optimized for off-line power supply applications such as lcd tv, audio and printers, where an auxiliary power supply for the ic is provided. the digital frequency reduction with decreasing load enables a quasi-resonant operation till very low load. as a result, the system efficiency is significantly improved compared to a free running quasi resonant converter implemented with maximum switching frequency limitation only. in addition, numerous protection functions have been implemented in the ic to protect the system and customize the ic for the chosen application. all of these make the ICE2QS02G an outstanding product for real quasi-resonant flyback converter in the market. typical application snubber gnd fb vins vcc zc gate cs control unit gate driver current limitation ICE2QS02G r cs tl431 optocoupler r b1 r b2 r c1 c c1 c c2 r ovs2 r ovs1 r zc2 r zc1 c zc w p w s w a d o c o l f c f v o c fb c ps c ds c bus auxiliary supply mains input voltage r vins2 r vins1 c bl bl vcc power management digital process block global protection block current mode control zero crossing detection r bl type package ICE2QS02G pg-dso-8-8
quasi-resonant pwm controller ICE2QS02G table of contents page version 2.0 4 13 june 2008 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 representative block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3.1 digital frequency redu ction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3.1.1 up/down counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3.1.2 zero crossing (zc counter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3.1.3 ring suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3.1.4 switch on determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3.2 switch off determinatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.1 foldback point correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.4 current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.5 soft start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.6 foldback point correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.7 digital zero crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.8 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.9 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
version 2.0 5 13 june 2008 quasi-resonant pwm controller ICE2QS02G pin configuration and functionality 1 pin configuration and functionality 1.1 pin configuration 1.2 package figure 1 pin configuration pg-dso-8-8 (top view) 1.3 pin functionality bl (adjustable blanking time) by connecting a capacitor and a resistor in parallel between this pin and the ground, the blanking time for can be fully adjusted, as well as the restart time. this allows the system to face a sudden power surge for a short period of time without triggering the overload protection. once the protection triggered, the ic will restart using the internal soft-start circuit, after a period of time fixed by the external resistance and capacitor. zc (zero crossing) three functions are incorporated at the zc pin. first, during mosfet off time, the full demagnetization of the transformer is detected when the zc voltage falls below v zcct (100mv). second, after the mosfet is turned off, an output overvoltage fault will be assumed if v zc is higher than v zcovp (4.5v). finally, during the mosfet on time, a current depending on the main input voltage flows out of this pin. information on this current is then used to adjust the maximum current limit. more details on this function are provided in section 3.4. fb (feedback) usually, an external capacitor is connected to this pin to smooth the feedback voltage. internally, this pin is connected to the pwm signal generator for switch-off determination (together with the current sensing signal), and to the digital signal processing for the frequency reduction with decreasing load during normal operation. additionally, the openloop/overload protection is implemented by monitoring the voltage at this pin. cs (current sensing) this pin is connected to the shunt resistor for the primary current sensing, externally, and the pwm signal generator for switch-off determination (together with the feedback voltage), internally. moreover, short- winding protection is realised by monitoring the v cs voltage during on-time of the main power switch. vins (input voltage sensing) the voltage at this pin is used for mains undervoltage protection. the protecti on is triggered, once v vins drops below 1.25v. for a stable operation, a hysteresis operation is ensured using an internal current source (see section 3.5). when the v vins exceeds the hysteresis point, the system resumes its operation with a soft-start. gate (gate drive output) the gate pin is the output of the internal driver stage, which has a rise time of 100ns and a fall time of 25ns when driving a 2.2nf capacitive load. vcc (power supply) the vcc pin is the positive s upply of the ic and should be connected to an external auxiliary supply. gnd (ground) this is the common ground of the controller. pin symbol function 1 bl blanking time 2 zc zero crossing 3 fb feedback 4 cs primary current sensing 5 vins input voltage sensing 6 gate gate driver output 7 vcc controller supply voltage 8 gnd controller ground 1 4 3 2 bl zc fb cs 8 5 6 7 gnd vcc gate vins
quasi-resonant pwm controller ICE2QS02G representative block diagram version 2.0 6 13 june 2008 2 representative block diagram figure 2 representative block diagram & g10 v zcovp c9 v zcct c8 48ms clock zc counter up/down counter comparator t zcovp v zcrs c10 counter control ring suppression d1 i zc v dd voltage reference internal bias v ref undervoltage lockout 12v 11v c2 v bll c3 v blh & g3 1 g2 r s q g1 r s q g4 v dd i bl r fb 25k ? 2pf v ref c5 c6 c7 level adjustment v fbolp c4 i vinshys c1 v vinsth cs gnd bl vins vcc fb zc soft start control & g5 clock pwm op pwm comparator v pwm q t cssw g pwm c11 v cssw leading edge blanking time t leb foldback point correction gate & g12 1 g9 1 g6 t onmax t permax gate drive r s q g8 r s q g11 c12 1 g7 10k ? 2pf d2
quasi-resonant pwm controller ICE2QS02G funtional description version 2.0 7 13 june 2008 3 funtional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 general ICE2QS02G is a second generation quasi-resonant controller ic developed by infineon technologies. its application is mainly fo cused on power systems with external standby power control, such as in lcd tv or printer applications. hence, the required ic vcc voltage for the ic is here drawn from an auxiliary power supply. the digital frequency reduction system implemented in this ic allows highly efficient power converter throughout all the load range. this ic possesses also numerous adjustable protection features, in order to protect the system and customize the ic for the target applications. 3.2 startup phase at the time t on , the ic begins to operate with a soft- start.by this soft-start t he switching stresses for the switch, diode and transformer are minimised. the soft- start implemented in ICE2QS02G is a digital time- based function. the preset soft-start time is 16ms with 4 steps. the internal reference for the feedback voltage begins at 1.8v and with an in crement of 0.55v for each following step. during soft start, the over load protection function is disabled. figure 3 soft-start control voltage versus time 3.3 pwm control the pwm controller during normal operation consists of a digital signal processing circuit including an up/ down counter, a zero-crossing counter (zc counter) and a comparator, and an analog circuit including a current measurement unit and a comparator. the switch-on and switch-off time points are each determined by the digital circuit and the analog circuit, respectively. as input information for the switch-on determination, the zero-crossing input signal and the value of the up/down counter are needed, while the feedback signal v fb and the current sensing signal v cs are necessary for the switch-off determination. details about the full operation of the pwm controller in normal operation are illustrated in the following paragraphs. 3.3.1 digital frequency reduction as mentioned above, the digital signal processing circuit consists of an up/down counter, a zc counter and a comparator. these three parts are key to implement digital frequency reduction with decreasing load. in addition, a ringing suppression time controller is implemented to avoid mistriggering by the high frequency oscillation, when the output voltage is very low under conditions such as soft start or output short circuit . functionality of these parts is described as in the following. 3.3.1.1 up/down counter the up/down counter stores the number of the zero crossing to be ignored before the main power switch is switched on after demagnetisation of the transformer. this value is fixed according to the feedback voltage, v fb , which contains information about the output power. indeed, in a typical peak current mode control, a high output power results in a high feedback voltage, and a low output power leads to a low regulation voltage. hence, according to v fb , the value in the up/ down counter is changed to vary the power mosfet off-time according to the output power. in the following, the variation of the up/down counter value according to the feedback voltage is explained. the feedback voltage v fb is internally compared with three threshold voltages v fbzl , v fbzr1 and v fbzh , at each clock period of 48ms. the up/down counter counts then upward, keep unchanged or count downward, as shown in table 1. table 1 operation of the up/down counter t on 4 8 12 16 1.8 2.35 2.9 3.45 4.00 vsst (v) time(ms) v fb up/down counter action always lower than v fbzl count upwards till 7 once higher than v fbzl , but always lower than v fbzh stop counting, no value changing once higher than v fbzh , but always lower than v fbzr1 count downwards till 1 once higher than v fbzr1 set up/down counter to 1
quasi-resonant pwm controller ICE2QS02G funtional description version 2.0 8 13 june 2008 in the ICE2QS02G, the number of zero crossing is limited to 7. therefore, the counter varies between 1 and 7, and any attempt beyond this range is ignored. when v fb exceeds v fbzr1 voltage, the up/down counter is initialised to 1, in order to allow the system to react rapidly to a sudden load increase. the up/down counter value is also intialised to 1 at the start-up, to ensure an efficient maximum load start up. figure 4 shows some examples on how up/down counter is changed according to the feedback voltage over time. the use of two different thresholds v rl and v rh to count upward or downward is to prevent frequency jittereing when the feedback voltage is close to the threshold point. however, for a stable operation, these two thresholds must not be affected by the foldback current limitation (see section 3.4.1), which limits the v cs voltage. hence, to prevent such situation, the threshold voltages, v fbzl and v fbzh , are changed internally depending on the line voltage levels. figure 4 up/down counter operation 3.3.1.2 zero crossing (zc counter) in the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a rc network, which provides a time delay to the voltage from the auxiliary winding. internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller. during on-state of the power switch a negative voltage applies to the zc pin. through the internal clamping network, the voltage at the pin is clamped to around - 0.2v. the zc counter has a minimum value of 0 and maximum value of 7. after mosfet is turned off, every time when the falling voltage ramp of on zc pin crosses the v zcct (100mv) threshold, a zero crossing is detected and zc counter will increase by 1. it is reset to 0 every time after the gate output is changed to high. the voltage v zc is also used for the output overvoltage protection. once the voltage at this pin is higher than the threshold v zcovp (4.5v) during off-time of the main switch, the ic is latched off after a fixed blanking time (t zcovp ). to achieve the switch-on at minimum value of drain- source voltage, the voltage from the auxiliary winding is fed to a time delay network (the rc network consists of r zc1 , r zc2 and c zc as shown in typical application circuit) before it is applied to the zero-crossing detector through the zc pin. the needed time delay to the main oscillation signal ? t should be approximately one fourth of the oscillation period (by transformer primary inductor and drain-source capacitor) minus the propagation delay from thedetected zero-crossing to the switch-on of the main switch t delay , theoretically: [1] this time delay should be matched by adjusting the time constant of the rc network which is calculated as: [2] 3.3.1.3 ringing suppression time after mosfet is turned on, there will be some oscillation on v ds , which will also appear on the voltage on zc pin. to avoid that the mosfet is turned on mistriggerred by such oscillations, a ringing suppression timer is implemented. the time is dependent on the voltage v zc . when the voltage v zc is lower than the threshold v zcrs , a longer preset time applies, while a shorter time is set when the voltage v zc is higher than the threshold. 3.3.1.4 switch on determination after the gate drive goes to low, it can not be changed to high during ring suppression time. after ring suppression time, the gate drive can be turned on when the zc counter value is higher or equal to up/down counter value. however, it is also possibl e that the oscillation between primary inductor and drain-source capacitor attenuates very fast and ic can not detect enough zero crossings and zc counter value will not be high enough to turn on the gate drive. in this case, a maximum switching period (t permax ) is implemented. after the specified period since last time gate is turned on, the gate drive will be turned on again regardless of the counter values and v zc . this function can effectively prevent the 1 case 3 case 2 case 1 up/down counter n n+1 n+2 n+2 n+2 n+2 n+1 n n-1 4 5 6 6 6 6 5 4 3 1 1 2 3 4 4 4 4 3 2 1 7 7 7 7 7 7 6 5 4 t t v fb v fbzr1 v fbzh v fbzl clock t=48ms 1 ? t t osc 4 ------------ t delay ? = td c zc r zc1 r zc2 ? r zc1 r zc2 + -------------------------------- - ? =
quasi-resonant pwm controller ICE2QS02G funtional description version 2.0 9 13 june 2008 switching frequency from going lower than 20khz, otherwise which will cause audible noise in most cases. 3.3.2 switch off determination in the converter system, the primary current is sensed by an external shunt resistor, which is connected between low-side terminal of the main power switch and the common ground. the sensed voltage across the shunt resistor v cs is applied to an internal current measurement unit, and its output voltage v 1 is compared with the regulation voltage v fb . once the voltage v 1 exceeds the voltage v fb , the output flip-flop is reset. as a result, the main power switch is switched off. the relationship between the v 1 and the v cs is described by: [3] in addition, there is a maximum on time, t onmax , limitation implemented in the ic. once the gate drive has been in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from going too low because of long on time. 3.4 current limitation there is a cycle by cycle curre nt limitation realized by the current limit comparator to provide an overcurrent detection. the source cu rrent of the mosfet is sensed via a sense resistor r cs . by means of r cs the source current is transformed to a sense voltage v cs which is fed into the pin cs. if the voltage v cs exceeds an internal voltage limit, adjusted according to the mains voltage, the comparator immediately turns off the gate drive. to prevent the current limitation process from distortions caused by leading edge spikes, a leading edge blanking time (t leb ) is integrated in the current sensing path. a further comparator is implemented to detect dangerous current levels (v cssw ) which could occur if one or more transformer windings are shorted or if the secondary diode is shorted. to avoid an accidental latch off, a spike blanking time of t cssw is integrated in the output path of the comparator . 3.4.1 foldback point correction when the main bus voltage increases, the switch on time becomes shorter and therefore the operating frequency is also increased. as a result, for a constant primary current limit, the maximum possible output power is increased, which the converter may have not been designed to support. to avoid such a situation, the internal foldback point correction circuit varies the v cs voltage limit according to the bus voltage. this means the v cs will be decreased when the bus voltage increases. to keep a constant maximum input power of the converter, the required maximum v cs versus various input bus voltage can be calculated, which is shown in figure 5. figure 5 variation of the vcs limit voltage according to the izc current according to the typical application circuit, when mosfet is turned on, a negative voltage proportional to bus voltage will be coupled to auxiliary winding. inside ICE2QS02G, an internal circuit will clamp the voltage on zc pin to nearly 0v. as a result, the current flowing out from zc pin can be calculated as [4] when this current is higher than i zc_1 , the amount of current exceeding this threshold is used to generate an offset to decrease the maximum limit on v cs . since the ideal curve shown in figure 5 is a nonlinear one, a digital block in ICE2QS02G is implemented to get a better control of maximum output power. additional advantage to use digital circuit is the production tolerance is smaller compared to analog solutions. the typical maximum limit on v cs versus the zc current is shown in figure 6. figure 6 v cs-max versus i zc v 1 3.3 v cs ? 0.7 + = 0.6 0.7 0.8 0.9 1 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 vin(v) vcs-max(v) i zc v bus n a r zc1 n p ------------------------ = 0.6 0.7 0.8 0.9 1 300 500 700 900 1100 1300 1500 1700 1900 2100 iz c(ua) vcs-max(v)
quasi-resonant pwm controller ICE2QS02G funtional description version 2.0 10 13 june 2008 3.5 protection functions ICE2QS02G provides various protection functions. the following table summarizes these protection functions. table 2 protection features during normal operation, the vcc voltage is continuously monitored. in case of a vcc undervoltage, the ic is reset and the main power switch is kept off. the overload and open loop protection contains an adjustable blanking time and variable restart time. such an adjustable buffer time is indeed, useful, for applications that usually work in low output power, but require a short duration of high output poweroccasionally. here, when the regulation voltage, v fb exceeds the threshold voltage of v fbolp , an internal current source of i bl starts charging the external capacitor c bl . this current source turns off only when the capacitor voltage, v bl reaches v blh or when v fb decreases below v fbh . once v bl exceeds v blh , the overload/openloop protection is triggered by turning off the gate signal, and pulling high the feedback voltage. from this time, c bl slowly discharges through the external resistance r bl . when v bl drops below v bll , the ic restarts its operation beginning with soft-start. the charging time and the discharging time of the capacitor c bl , fix respectively the openloop/overload protection blanking time and the restart time of the ic. one example about how this protection works is shown in figure 7. figure 7 over load protection and timers the blanking time for over load protection can be calculated using equation [5]. [5] the restart time for over load protection can be calculated using equation [6]. [6] during the switch off time, the voltage at the zero- crossing pin, zc, is monitored for output overvoltage detection. if this voltage is higher than the preset threshold v zcovp , the ic enters latch-off mode. if the voltage at the current sensing pin is higher than the preset threshold v cssw of 1.68v during the on-time of the power switch, the ic is latched off. this consitutes a short winding protection. finally, this ic has an adjustable main undervoltage detection system. given the resistances r vins1 and r vins2 connected to the vins pin, the main turn off voltage is given by equation [7]. [7] for system stability, a hyster esis is implemented in the main undervoltage protection using an internal current source i vins , so that the main turn on voltage is given by equation [8]. [8] everytime ic recovers from a mains undervoltage protection, ic will begin with a soft start. vcc undervoltage latch off overload/openloop protection auto restart main undervoltage protection block gate recover with soft start output overvoltage latch off short winding latch off v fb v bl v gate 4.5v 0.5v 3.9v t t t t restart t olp t restart t ss t olp t ss t olp r ? bl c bl 1 v blh i bl r bl ------------------ ? ?? ?? ln = t restart r bl ?c bl v bll v blh ------------- ?? ?? ln = v busoff v vinsth r vins1 r vins2 + r vins2 ----------------------------------------- ? = v buson v busoff i vinshys r vins 1 ? + =
quasi-resonant pwm controller ICE2QS02G electrical characteristics version 2.0 11 13 june 2008 4 electrical characteristics note: all voltages are measured with respect to ground (pin 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 7 (vcc) is discharged before assembling the application circuit. 4.2 operating range note: within the operating range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc -0.3 27 v vins voltage v vins -0.3 5.0 v bl voltage v bl -0.3 5.0 v fb voltage v fb -0.3 5.0 v zc voltage v zc -0.3 5.0 v cs voltage v cs -0.3 5.0 v gate voltage v gate -0.3 10.0 v junction temperature t j -40 125 c storage temperature t s -55 150 c thermal resistance junction-ambient r thja (dso) - 185 k/w pg-dso-8 esd capability v esd - 2 kv human body model 1) 1) according to eia/jesd22-a114-b (disc harging a 100pf capacitor through a 1.5k ? series resistor) parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccuvp 25 v junction temperature t jcon -25 125 c
quasi-resonant pwm controller ICE2QS02G electrical characteristics version 2.0 12 13 june 2008 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range t j from ? 25 o c to 125 o c. typical values represent the median values, which are related to 25c. if not other wise stated, a supply voltage of v cc = 18 v is assumed. 4.3.2 internal voltage reference parameter symbol limit values unit test condition min. typ. max. start-up current i vccstart -300- av vcc = 11v supply current in normal operation i vccop - 1.5 - ma output low i fb = 0 supply current during latch-off mode i vcclo -300- ai fb = 0 vcc turn-on threshold v vccon 11.3 12.0 12.7 v vcc turn-off threshold v vccoff -11.0-v vcc turn-on/off hysteresis v vcchys 0.6 1 1.4 v parameter symbol limit values unit test condition min. typ. max. internal reference voltage v ref 4.90 5.00 5.10 v measured at pin fb i fb =0
quasi-resonant pwm controller ICE2QS02G electrical characteristics version 2.0 13 13 june 2008 4.3.3 pwm section 4.3.4 current limit 4.3.5 soft start 4.3.6 foldback point correction parameter symbol limit values unit test condition min. typ. max. regulation pull-up resistor r fb 13 20 30 k ? pwm-op gain g pwm 3.15 3.3 3.47 offset for voltage ramp v pwm 0.6 0.7 0.85 v parameter symbol limit values unit test condition min. typ. max. peak cuurent limitation in normal operation v csth 0.94 1.02 1.10 v leading edge blanking t leb 180 280 450 ns parameter symbol limit values unit test condition min. typ. max. soft-start time t ss 11.8 16 - ms soft-start time step 1) t sss 4ms internal regulation voltage at first step 1) v ss1 -1.8-v internal regulation voltage step at soft start 1) v sss -0.55-v parameter symbol limit values unit test condition min. typ. max. fbc start point v cs_fbc_s -1.02-vi zc =0.5ma cs threshold minimum v cs_fbc_min -0.65-vi zc =1.8ma
quasi-resonant pwm controller ICE2QS02G electrical characteristics version 2.0 14 13 june 2008 4.3.7 digital zero crossing 4.3.8 protection parameter symbol limit values unit test condition min. typ. max. zero crossing threshold voltage v zcct 50 100 170 mv maximum current out from zero crossing pin 1) i zcmax 2.5--ma threshold to set up/down counter to one v fbzr1 3.78 3.9 4 v threshold for downward counting at low line v fbzhl 3.10 3.2 3.32 v threshold for upward counting at low line v fbzll 2.38 2.5 2.62 v threshold for downward counting at high line v fbzhh 2.55 2.7 2.90 v threshold for upward counting at highline v fbzlh 2.18 2.3 2.42 v zc current for ic switches threshold to high line i zchl -1.3-ma zc current for ic switches threshold to low line i zcll -0.8-ma counter time 1) 1) the parameter is not subjected to production test - verified by design/characterization t count 48 ms parameter symbol limit values unit test condition min. typ. max. overload or open loop detection threshold for olp protection at fb pin v fbolp 4.4 4.5 4.6 v charging current at bl pin i bl 12 20 28 a threshold for adjustable overload blanking time v blh 3.80 3.9 4.01 v threshold for adjustable restart time v bll 0.4 0.5 0.6 v output overvoltage detection threshold at the zc pin v zcovp 4.4 4.5 4.6 v blanking time for output overvoltage protection 1) t zcovp -100- s threshold for short winding protection v cssw 1.63 1.68 1.78 v blanking time for short winding protection t cssw -190-ns
quasi-resonant pwm controller ICE2QS02G electrical characteristics version 2.0 15 13 june 2008 4.3.9 gate driver main undervoltage protection threshold v vinsth -1.25-v main undervoltage protection hysteresis current source i vinshys 8.8 15 20 a minimum ringing suppression time t zcrs1 1.87 2.8 3.5 sv zc > v zct2 maximum ringing suppression time t zcrs2 18 25 32 sv zc < v zct2 ringing suppression threshold v zcrs -0.7-v maximum gate on time t onmax 25 30.0 35.1 sv fb >4.3v, v cs =0 maximum switching period t permax 42 50.0 57 s 1) the parameter is not subjected to production test - verified by design/characterization parameter symbol limit values unit test condition min. typ. max. output voltage at logic low v gatelow --1.0vi out = 20ma; v vcc =18v output voltage at logic high v gatehigh 9.0 10.0 - v i out = -20ma; v vcc =18v output voltage active shut down v gateasd --1.0v v v vcc = 7v i out = 20ma rise time t rise -70-nsc out = 2.2nf; v gate 2v ... 8v fall time t fall -30-nsc out = 2.2nf; v gate 8v ... 2v
quasi-resonant pwm controller ICE2QS02G outline dimension version 2.0 16 13 june 2008 5 outline dimension figure 8 pg-dso-8-8 *dimensions in mm pg-dso-8 ( plastic dual small outline)
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